A half bridge circuit, an H bridge circuit, a three-phase bridge circuit (hereinafter, collectively referred to as a “switching output circuit”) using a power transistor are used in various electronic circuits including a motor driver, an inverter, and a converter.
FIG. 1 is a circuit diagram of a switching output circuit reviewed by the present inventors. A switching output circuit 100r includes a bridge circuit 106 of an output stage and a gate driving circuit 108r for driving the bridge circuit 106. The bridge circuit 106 includes a high-side transistor M1 installed between an input power line (hereinafter, also simply referred to as an “input line”) 102 and an output line 104, and a low-side transistor M2 installed between the output line 104 and a ground line 103. The high-side transistor M1 and the low-side transistor M2 are configured with an N-channel MOSFET or an IGBT. For example, an input voltage VIN is tens of volts to hundreds of volts (here, 600 V), and an output voltage VOUT is switched between a ground voltage 0 V as a low level and 600 V as a high level.
The gate driving circuit 108r complementarily switches the high-side transistor M1 and the low-side transistor M2 based on control signals SIN_H and SIN_L.
In order to turn on the high-side transistor M1, it is required to apply a voltage higher than the input voltage VIN of 600 V to a gate of the high-side transistor M1. When a voltage (e.g., 20 V) lower than 600 V is supplied as a power supply voltage VCC of the gate driving circuit 108r, so-called bootstrap circuits D1 and C1 are used. A switching terminal (VS terminal) of the gate driving circuit 180r is connected to a source of the high-side transistor M1 and a drain of the low-side transistor M2. One end of the capacitor C1 is connected to the VS terminal, and the other end thereof is connected to a bootstrap terminal VB of the gate driving circuit 180r. A cathode of the diode D1 is connected to the VB terminal and an anode thereof is connected to the VCC terminal. As the high-side transistor M1 is switched, the capacitor C1 is charge-pumped, so that a DC voltage higher than that of the VS terminal by VCC-VF is generated at the VB terminal VF is a forward voltage of the diode D1. A level shifter 112, a waveform shaper 114, and a high-side driver 116, which will be described later, are operated by a voltage VB (called a “bootstrap voltage”) of the VB terminal as a power supply voltage.
The control signal SIN_H is a digital signal for instructing ON/OFF of the high-side transistor M1, and a high level thereof corresponds to ON of the high-side transistor M1 and a low level thereof corresponds to OFF of the high-side transistor M1. An edge detection circuit 110 detects a positive edge and a negative edge of the control signal SIN_H, and asserts a set pulse LV_S at a positive edge (set to high level) and asserts a reset pulse LV_R at a negative edge (set to high level). The edge detection circuit 110 operates by receiving the power supply voltage VCC, and thus, the high-level voltages of the set pulse LV_S and the reset pulse LV_R become the power supply voltage VCC.
The level shifter 112 level-shifts the high level voltages of the set pulse LV_S and the reset pulse LV_R to the bootstrap voltage VB to generate a set pulse HV_S and a reset pulse HV_R.
The waveform shaper 114 generates a driving pulse SP that transitions to a first level (e.g., a high level) in response to the set pulse HV_S, and that transitions to a second level (e.g., a low level) in response to the reset pulse HV_R. The high-side driver 116 switches the high-side transistor M1 based on the driving pulse SP.
The low-side driver 118 switches the low-side transistor M2 based on the control signal SIN_L input to a LIN terminal.
FIG. 2 is a circuit diagram illustrating the level shifter 112 and the waveform shaper 114 reviewed by the present inventors. The level shifter 112 includes high voltage N channel MOS transistors M11 and M12, resistors R11 to R14, and diodes D11 and D12.
The waveform shaper 114 mainly includes an inverting circuit 120 and an RS flip-flop 122. The outputs HV_S and HV_R after being level-shifted by the level shifter 112 of FIG. 2 become logics inverted from the input pulses LV_S and LV_R prior to level shifting (in the present disclosure, # indicates an inverted logic). Thus, the inverting circuit 120 logically inverts the pulses HV_S and HV_R to return them to the same logic levels as the original pulses LV_S and LV_R, respectively. The RS flip-flop 122 receives pulses A and B, which have passed through the inverting circuit 120, to generate a driving pulse SP.
In a three-phase inverter, a certain phase is exposed to noise due to a counter electromotive force of the other phases. Due to this noise, even if both the set pulse LV_S and the reset pulse LV_R are not asserted, the set pulses HV_S and HV_R may be caused to change by fluctuation in the voltage of the VS terminal or the VB terminal.
FIG. 3 is a waveform diagram illustrating an influence of noise in the level shifter 112 and the waveform shaper 114. In the inverted set pulse #HV_S and the inverted reset pulse #HV_R, negative edges are sharply changed, while positive edges gradually transition due to an influence of parasitic capacitance (capacitance between a drain and a source) of the transistors M11 and M12.
Due to the influence of noise, even though the original set pulse LV_S and the reset pulse LV_R are at a low level (negated), both the inverted set pulse #HV_S and the inverted reset pulse #HV_R may be caused to transition to a low level, and thus, both of the pulses A and B outputted from the inverting circuit 120 transition to a high level. That is, a problem arises in that, when the RS flip-flop 122 is a set dominant type, the driving pulse SP having a low level may transition to a high level, and when the RS flip-flop 122 is a reset dominant type, the driving pulse SP having a high level may transition to a low level.
In addition, time constants of positive edges of the inverted set pulse #HV_S and the inverted reset pulse #HV_R is determined by parasitic capacitance of the transistors M11 and M12 and resistance values of the resistors R11 and R12, so that a situation in which time constants of the set side and the reset side are different from each other by element variations can be caused. This makes countermeasures of the set pulse A and the reset pulse B due to noise more difficult.
Further, the problems described herein should not be considered as generally recognized by a person skilled in the art but recognized by the present inventors independently. Also, the problem can arise in various bridge circuits, without being limited to the three-phase inverter.